Master of Engineering in Integrated Circuit Design
The global shortage of chip design and verification engineers is structural, the work is routinely performed remotely, and the barrier to African participation is training rather than capital. This programme converts engineering and computi...
The four facts
What you actually need to compare
- Award and entry
- MEng
- A
- Duration and mode
- 18 months (3 semesters)
- Hybrid. Includes 12 months of paid, assessed cooperative education.
- Cost
- UGX 3,600,000 per year
- Tier 2 laboratory classification. Includes UGX 600,000 annual laboratory premium.
- Outcome targeted
- Digital design engineer, verification engineer, physical design and timing engineer
- Reviewed by 2031. If the thesis stops holding, the programme is reviewed.
Pricing Model 5.1 · The Forward Standard
Master of Engineering in Integrated Circuit Design fee
UGX 3,600,000 per year
- Laboratory tier
- Tier 2
- Annual premium
- UGX 600,000
- Per semester
- UGX 1,800,000
- Whole programme
- UGX 5,400,000
- Approximate USD
- ≈ USD 1,421
What this fee includes
- Teaching, practice tutoring, assessment and competency verification
- The Amagezi platform and AI tutor around the clock
- All learning materials
- Every examination, including first resits
- Identity card, library, guild, sports and basic wellbeing
- Co-op placement matching and the Capability Passport
- Graduation and the statutory NCHE fee
- Online application
Employment thesis
What this programme is designed to produce
Forward publishes the destination of every programme before you enrol. If the thesis stops holding, the programme is reviewed and, where necessary, retired. Next review: 2031.
Roles
- Digital design engineer
- verification engineer
- physical design and timing engineer
- analogue and mixed signal designer
- design for test engineer
- FPGA and accelerator engineer.
Employer types
- Global semiconductor design houses and their offshore design centres
- fabless start ups
- electronics manufacturers
- research institutes
- and remote contract design services.
Target outcomes we hold ourselves to
- Roles in this field are among the highest paid technical positions accessible from Africa and are routinely staffed remotely.
Compulsory · The Forward Core
How the Core works →Every Forward programme, including this one, carries the same five cross-cutting requirements. They are graded, not optional.
- AI Fluency
- Quantitative Reasoning
- Ethics and African Context
- Human-Advantage Skills
- Enterprise
Includes 12 months paid work-integrated learning
Am I eligible?
Check yourself against the published requirements
7 questions written specifically for Master of Engineering in Integrated Circuit Design. Every answer is checked against a requirement Forward has published, and the result tells you which page that requirement comes from. Indicative only, the admissions office decides on your full file.
What is the highest qualification you hold?
Curriculum structure
The same degree, in both pathways
Every Forward programme is published in both pathways: Path One, the term plan of two six-month terms, and Path Two, the block sequence of twelve four-week blocks. Same competencies, same assessments, same award. Toggle to see this programme in each.
Path One term plan shown
Path One · The Term Model
| Code | Course | CU | Hours |
|---|---|---|---|
| FDC 501 | Applied Intelligence for Professionals Both | 4 | 2-2-0 |
| FDC 502 | Research Evidence and Method Both | 4 | 2-2-0 |
| IEM 510 | Advanced Digital Design and Microarchitecture Performance | 6 | 3-2-4 |
| IEM 511 | CMOS Analogue Circuit Design Performance | 6 | 3-2-4 |
| IEM 512 | Hardware Description Languages and Design Methodology Performance | 5 | 2-2-4 |
| IEM 513 | Semiconductor Devices and Technology Both | 5 | 3-2-2 |
| Code | Course | CU | Hours |
|---|---|---|---|
| FDC 503 | Governance, Ethics and Leadership of Intelligent Systems Both | 4 | 2-2-0 |
| IEM 520 | Functional Verification, Coverage and Formal Methods Performance | 7 | 4-2-4 |
| IEM 521 | Physical Design and Timing Closure Performance | 7 | 4-2-4 |
| IEM 522 | Design for Test, Yield and Reliability Both | 5 | 3-2-2 |
| IEM 523 | Low Power and Mixed Signal Integration Performance | 5 | 2-2-4 |
| Code | Course | CU | Hours |
|---|---|---|---|
| IEM 530 | Tapeout Project: Silicon Design, Submission and Characterisation Performance | 20 | 0-2-38 |
| IEM 531 | Accelerator and Domain Specific Architecture Both | 5 | 3-2-2 |
| IEM 532 | Semiconductor Industry, Supply Chain and Careers Objective | 5 | 4-2-0 |
Total credit units: 88
Curriculum source
Forward University Curriculum Compendium
Assessment
Coursework + project + integrated exam
Work-integrated learning
12 months paid co-operative education
Your week at Forward
A typical week on Master of Engineering in Integrated Circuit Design
Path One, the Term Model: your own pace across a six-month term, one live session a week, short flexible lessons, and assessment on demand.
Monday
Tuesday
Wednesday
Thursday
Friday
Curriculum explorer
Drill into the degree, step by step
Choose a study path, then a year, then a term or block, then a course. Credit totals add up as you go, and every course shows what comes before it and what it unlocks.
Step 1, choose a year
Step 2, choose a term
TERM 1 (SIX MONTHS) | FORMERLY SEMESTER 1
Year 1 · this step is worth 30 CU
Cumulative
30
Programme total
90
30 CU of 90 CU completed by the end of this step (33%)
Step 3, choose a course
Pick a course to see the detail
Credits, assessment, prerequisites and what each course unlocks later.
The twelve Forward capabilities
What this programme develops in you
Every Forward degree develops the same twelve cross-cutting capabilities. The profile below is the level this programme is designed to develop and verify by graduation, on the four-level scale in Part B2 of the Curriculum Compendium. Every claim above Level 2 is verified by someone other than the teaching lecturer.
- C1Intelligent Systems FluencyLevel 4 of 4, Leading
- C2Quantitative and Evidential Reasoning CriticalLevel 4 of 4, Leading
- C3Ethical and Contextual JudgementLevel 3 of 4, Independent
- C4Communication and PersuasionLevel 4 of 4, Leading
- C5Disciplinary Mastery CriticalLevel 4 of 4, Leading
- C6Technical Production and Craft CriticalLevel 4 of 4, Leading
- C7Problem Framing and Systems ThinkingLevel 4 of 4, Leading
- C8Collaboration and Multidisciplinary TeamingLevel 3 of 4, Independent
- C9Enterprise, Value and Commercial LiteracyLevel 3 of 4, Independent
- C10Professional Conduct and Workplace PerformanceLevel 4 of 4, Leading
- C11Learning to Learn and Adaptive Capacity CriticalLevel 4 of 4, Leading
- C12Stewardship and Public ContributionLevel 3 of 4, Independent
Critical capabilities for this programme: Quantitative and Evidential Reasoning · Disciplinary Mastery · Technical Production and Craft · Learning to Learn and Adaptive Capacity. A graduate cannot pass out of this programme below the stated level on any capability marked critical.
Programme Learning Outcomes
What you will be able to do
Each outcome is assessed, and each is tagged with the Forward capabilities it is verified against.
- PLO 1Specify, design and implement digital integrated circuits from architecture to gate level.
- PLO 2Construct and execute an industrial standard verification environment with coverage closure.
- PLO 3Complete physical implementation including floorplanning placement, routing and timing closure.
- PLO 4Design analogue and mixed signal blocks to specification.
- PLO 5Apply design for test and reason about yield, reliability and manufacturability.
- PLO 6Manage a tapeout project including schedule, sign off criteria and risk.
Why this programme exists
The global shortage of chip design and verification engineers is structural, the work is routinely performed remotely, and the barrier to African participation is training rather than capital. This programme converts engineering and computing graduates into employable design, verification and physical design engineers within eighteen months, culminating in a tapeout.
Admission requirements
A Bachelor's degree of at least Second Class Lower Division in electrical, electronic or computer engineering, computer science or physics, with demonstrated digital design or programming ability. Alternative pathways: Foundation Year, diploma entry with advanced standing, mature age entry and recognition of prior learning, all governed by Part A5 and Part G. Online applicants additionally complete the compulsory Digital Readiness orientation under Part D6.